Low-power CMOS technology DDC
United Semiconductor Japan (USJC) has joined forces with Centre Suisse d’Electronique et de Microtechnique (CSEM) to develop an ultra-low power IP platform targeting near/sub-threshold supply voltages in the USJC’s DDC (Deeply Depleted Channel) technology.
The challenge of near/sub-threshold circuit design
Near/sub-threshold design has become a very promising method for ultra low-power applications. It is well known that circuit performance in near/sub-threshold operations is highly sensitive to variations in the manufacturing process, circuit operation voltage and temperature (PVT). USJC’s DDC technology is the solution to overcome these problems.
Key features for DDC technology
(1) Variation Control and Flexible Performance Tuning
- Variation Control
Constant speed is achieved when temperature and process are varied.
Different speed modes enable to achieve optimum speed and power balance for applications.
Variation control and performance tuning can be realized by the body bias based control scheme (ADVbbFS).
(2) Ultra-Low Voltage Operation
ADVbbFS is applied to C55DDC SRAM Memory and stable operation is realized at near/sub-threshold voltage even with 6T SRAM-bit cells and the power operated at Vdd=0.6 V become dramatically lower.
C55DDC platform for near/sub-threshold circuits
USJC and CSEM will provide each IP block on the platform, which helps the customer to design ultra low power product. We will also provide ADVbbFS* which supports variation control and performance tuning through body biasing. IP information in detail is described in the brochure.
ADVbbFS* : Adaptive Dynamic Vbb control and Frequency Scaling
Customer can design based on the standard flow with two minor additions. USJC releases the C55DDC libraries that support Cadence and Synopsys EDA tools.
Design enablement support scheme
1)C55DDC Platform for IoT/Wearable Applications
2)C55DDC IP Line-up for near/sub-threshold circuits
Conference presentation materials and proceedings
1) 2019 ASSCC, Y. Zha, et al., “An Untrimmed PVT-Robust 12-bit 1-MS/s SAR ADC IP in 55nm Deeply Depleted Channel CMOS Process”
2)2019 CICC, Marc Pons, et al., “A 0.5V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS”
3)2019 PRIME, Christoph Thomas Müller, et al., “Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC”
4) 2012 IEDM, M. Hori, et al., “A Highly Integrated 65-nm SoC Process with Enhanced Power/Performance of Digital and Analog Circuits”
5) 2011 IEDM, L T. Clark, et al., “Advanced Channel Engineering Achieving Aggressive Reduction of VT Variation for Ultra-Low-Power Applications”