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FEOL (Front End of Line: substrate process, the first half of wafer processing)
4. LDD formation
To avoid adverse effects (such as slower operation speed) of transistor miniaturization, LDDs (Lightly Doped Drains, low density impurity drains) are formed.
LDDs are also called extensions.
N-LDD: N-type impurities (e.g., As+, P+) are implanted into n-MOS areas.
P-LDD: P-type impurities (e.g., B+) are implanted into p-MOS areas.
INDEX
4-1. n-LDD
p-A resist pattern is formed to cover the p-MOS area, and n-type impurities (e.g., phosphorus (P), arsenic (As)) are implanted in the n-MOS area.
After implantation, the resist pattern is removed.
4-2. p-LDD
A resist pattern is formed to cover the n-MOS area, and p-type impurities (e.g., boron (B)) are implanted in the p-MOS area.
After implantation, the resist pattern is removed.
Process Flow
FEOL (Front End of Line: substrate process, the first half of wafer processing)
|
1. Isolation|
2. Well and channel formation|
3. Gate oxidation and gate formation|
4. LDD formation|
5. Side wall spacers |
6. Source/drain|
7. Silicide |
8. Dielectric film|
9. Contact holes|
BEOL (Back End of Line: interconnect process, the second half of wafer processing)
|
10. Metal-1|
11. Metal-2|