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FEOL (Front End of Line: substrate process, the first half of wafer processing)
6. Source/drain
Sources and drains are formed in n-MOS areas and p-MOS areas. The shapes of sources and drains are the same because usual transistors are symmetric. Which is a source or a drain is defined depending on the connection direction of the power supply.
P-source/drain: P-type impurities (e.g., B+) are implanted into p-MOS areas.
N-source/drain: N-type impurities (e.g., As+, P+) are implanted into n-MOS areas.
6-1. p-source/drain
A resist pattern is formed to cover the n-MOS area, and p-type impurities (e.g., boron (B)) are implanted in the p-MOS area. After implantation, the resist pattern is removed.
6-2. n-source/drain
A resist pattern is formed to cover the p-MOS area, and n-type impurities (e.g., phosphorus (P), arsenic (As)) are implanted in the n-MOS area. After implantation, the resist pattern is removed.
Process Flow
FEOL (Front End of Line: substrate process, the first half of wafer processing)
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1. Isolation|
2. Well and channel formation|
3. Gate oxidation and gate formation|
4. LDD formation|
5. Side wall spacers |
6. Source/drain|
7. Silicide |
8. Dielectric film|
9. Contact holes|
BEOL (Back End of Line: interconnect process, the second half of wafer processing)
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10. Metal-1|
11. Metal-2|