Transistors are formed near the silicon wafer surface.
To ensure that each transistor operates independently, it is necessary to prevent interference with other neighboring transistors. Therefore, the regions where transistors are to be formed are isolated. There are a number of methods for this isolation.
The technique introduced here is called STI (Shallow Trench Isolation).

N-MOS transistors and p-MOS transistors are formed in a chip.
Impurities appropriate for n-MOS transistors and p-MOS transistors are respectively implanted into the Si surface at appropriate concentrations in the regions where the transistors are to be formed (n-MOS: p-well, n-channel; p-MOS: n-well, p-channel). In the case where transistors with two or more different voltages and characteristics are made, impurity implantation of different dopants/dosages is additionally performed.

This step is most important from the viewpoint of transistor characteristics.
A gate oxide film greatly influences the performance and reliability of a transistor, and should therefore be a high-density thin film uniformly distributed over the wafer surface.
Since the size of the gate formed may also greatly influence the performance of the transistor, strict dimensional control is necessary in both photo resist patterning and gate etching.
Gate electrodes are formed of polysilicon (polycrystalline silicon) by CVD.

To avoid adverse effects (such as slower operation speed) of transistor miniaturization, LDDs (Lightly Doped Drains, low density impurity drains) are formed.
LDDs are also called extensions.
N-LDD: N-type impurities (e.g., As+, P+) are implanted into n-MOS areas.
P-LDD: P-type impurities (e.g., B+) are implanted into p-MOS areas.

An oxide film is formed only at side wall portions of gates for LDD formation (above mentioned) and salicidation (described below) of gates, sources, and drains.
Side wall oxide film: A silicon oxide film is formed on the entire wafer surface.
Side wall etching: Anisotropic etching (vertical direction) is performed on the oxide film so that the oxide film may be left only on gate side walls.

Sources and drains are formed in n-MOS areas and p-MOS areas. The shapes of sources and drains are the same because usual transistors are symmetric. Which is a source or a drain is defined depending on the connection direction of the power supply.
P-source/drain: P-type impurities (e.g., B+) are implanted into p-MOS areas.
N-source/drain: N-type impurities (e.g., As+, P+) are implanted into n-MOS areas.

Silicide (compound of silicon with metal) is formed on gates (polysilicon), sources and drains (Si wafer) as three MOS transistor electrodes in order to reduce contact resistance to metal wiring layers to be formed later. This silicide formation also has the effect of lowering the resistance of each electrode.
Salicidation: A cobalt film is removed selectively by chemical etching (Self aligned silicide).

The interconnect process for connecting elements such as transistors starts from this step.
Dielectric film deposition: A thick silicon oxide film or the like is formed by CVD.
Dielectric film polishing: The silicon oxide film is polished for the film planarization of the wafer surface.

To connect electrodes such as gates, sources, and drains of transistors to metal wiring layers, contact holes are made in the dielectric film and filled with W (tungsten).
Plug-tungsten filling: Tungsten is deposited in contact holes.
Plug-tungsten polishing: The surface is polished to remove excess tungsten and leave tungsten only in the contact holes.

A dielectric film is deposited as an inter layer dielectric, a trench pattern is formed by photo resist patterning and etching, and trenches are filled with Cu (copper) metal by electroplating.
The method of filling only the trenches with Cu is called single damascene.
Metal-1 Cu filling: A Cu film is deposited in the trenches by electroplating.
Metal-1 Cu Polishing: Excess Cu is removed by surface polishing to leave Cu only in the trenches.

A dielectric film is deposited as an inter metal dielectric, a trench and via pattern is formed by photo resist patterning and etching, and trenches and vias are filled with Cu (copper) metal by electroplating. The method of filling trenches and vias with Cu at the same time is called dual damascene.
Metal-2 Cu filling: A Cu film is deposited in the trenches and the vias by electroplating.
Metal-2 Cu Polishing: Excess Cu is removed by surface polishing to leave Cu only in the trenches and the vias.